| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Implement make-compressible pass | Richard-Qin-X | 2026-08-25 | 1 | -0/+6 |
| * | [CodeGen] Implement RISC-V machine outlining | Richard-Qin-X | 2026-08-25 | 1 | -0/+20 |
| * | [CodeGen] Generate RISC-V macro fusion rules | Richard-Qin-X | 2026-08-22 | 1 | -1/+1 |
| * | [RISCV][GlobalISel] Select and expand global addresses | Richard-Qin-X | 2026-08-19 | 1 | -0/+5 |
| * | [MIR] Accept fixed-baseline LLVM syntax | Richard-Qin-X | 2026-08-11 | 1 | -0/+9 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -3/+3 |
| * | [MIR] Complete document parsing and printing | Richard-Qin-X | 2026-08-07 | 1 | -3/+36 |
| * | [MIR] Add compilation unit reference context | Richard-Qin-X | 2026-08-01 | 1 | -0/+175 |
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