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* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-261-0/+26
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-251-0/+6
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-251-0/+20
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-221-1/+1
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-191-0/+5
* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-131-52/+0
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-131-0/+1
* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-135-490/+0
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-123-4/+0
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-113-0/+19
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-091-3/+3
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-075-3/+260
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-042-0/+130
* [MIR] Add machine instruction lexerRichard-Qin-X2026-08-031-0/+181
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-011-0/+175
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 23:41:31 +0000