| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Implement Zcmp move merging | Richard-Qin-X | 2026-08-25 | 1 | -0/+1 |
| * | [RISCV] Match LLVM compressed stack frame lowering | Richard-Qin-X | 2026-08-24 | 1 | -0/+3 |
| * | [RISCV] Match LLVM frame lowering semantics | Richard-Qin-X | 2026-08-24 | 1 | -1/+13 |
| * | [CodeGen] Generate RISC-V macro fusion rules | Richard-Qin-X | 2026-08-22 | 1 | -0/+9 |
| * | [RISCV][GlobalISel] Select and expand global addresses | Richard-Qin-X | 2026-08-19 | 1 | -1/+14 |
| * | [RISCV][GlobalISel] Generate integer extension selections | Richard-Qin-X | 2026-08-17 | 1 | -0/+1 |
| * | [GlobalISel] Legalize G_ABDS and G_ABDU | Richard-Qin-X | 2026-08-14 | 1 | -0/+1 |
| * | [RISCV] Model non-ISA subtarget features | Richard-Qin-X | 2026-08-13 | 1 | -1/+34 |
| * | [RISCV] Split the GlobalISel target components | Richard-Qin-X | 2026-08-12 | 1 | -2/+38 |
| * | [RISCV] Honor invocation subtarget features | Richard-Qin-X | 2026-08-11 | 1 | -0/+47 |
