aboutsummaryrefslogtreecommitdiff
path: root/backend/include/rcc/Target/RISCV
Commit message (Expand)AuthorAgeFilesLines
* [RISCV][GlobalISel] Generate integer extension selectionsRichard-Qin-X2026-08-171-0/+1
* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-151-0/+1
* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-0/+2
* [GlobalISel] Legalize G_ABDS and G_ABDURichard-Qin-X2026-08-141-0/+1
* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-131-2/+8
* [RISCV] Model non-ISA subtarget featuresRichard-Qin-X2026-08-131-1/+34
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-2/+2
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-125-96/+46
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-121-6/+7
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-121-3/+0
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-121-2/+2
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-5/+0
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-121-0/+2
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-111-1/+2
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-113-0/+58
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-0/+63
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-101-0/+35
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-097-0/+219
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-093-0/+133
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-0/+12
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-091-0/+2
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-091-0/+2
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+1
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-081-0/+16
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-071-0/+43
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-2/+53
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+23
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 11:15:42 +0000