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* [GlobalISel] Narrow scalar shiftsRichard-Qin-X2026-08-151-0/+30
* [GlobalISel] Narrow scalar selectsRichard-Qin-X2026-08-151-0/+2
* [GlobalISel] Narrow scalar bitwise operationsRichard-Qin-X2026-08-151-0/+2
* [GlobalISel] Legalize constants and implicit definitionsRichard-Qin-X2026-08-151-0/+1
* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-1511-62/+322
* [GlobalISel] Legalize G_ABDS and G_ABDURichard-Qin-X2026-08-143-0/+7
* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-145-21/+32
* [RISCV] Legalize va_copy intrinsicsRichard-Qin-X2026-08-141-43/+36
* [MIR] Normalize explicit successor probabilitiesRichard-Qin-X2026-08-141-0/+3
* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-148-426/+532
* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-1413-8/+2333
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-135-77/+55
* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-135-13/+36
* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-132-0/+2
* [RISCV] Model non-ISA subtarget featuresRichard-Qin-X2026-08-131-1/+34
* [RISCV] Match LLVM register bank mappingsRichard-Qin-X2026-08-132-5/+18
* [MIR] Omit predictable successors in simplified outputRichard-Qin-X2026-08-131-0/+7
* [CodeGen] Remove duplicate analysis declarationsRichard-Qin-X2026-08-132-5/+0
* [IR] Sequence analysis registration movesRichard-Qin-X2026-08-131-2/+3
* [Tooling] Remove the duplicate output kindRichard-Qin-X2026-08-133-18/+6
* [Support] Centralize error context handlingRichard-Qin-X2026-08-131-0/+2
* [CodeGen] Remove the unused property queryRichard-Qin-X2026-08-131-1/+0
* [TableGen] Split the target description generatorRichard-Qin-X2026-08-132-0/+255
* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-138-61/+128
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-138-118/+176
* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-138-231/+167
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1342-826/+1142
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-139-416/+542
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-133-49/+62
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-126-104/+50
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-129-169/+229
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-126-54/+31
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-1210-30/+30
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-5/+0
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-124-30/+78
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-122-0/+2
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-124-5/+0
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+9
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-121-0/+2
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-111-1/+2
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-6/+0
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-114-1/+64
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-0/+63
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-119-3/+349
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1020-25/+754
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0917-0/+722
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0917-0/+1205
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0938-0/+1518
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-098-0/+177
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0920-19/+1160
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 11:31:53 +0000