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* [CMake] Remove unused clang-tidy file registrationRichard-Qin-X2026-08-288-32/+24
* [RISCV] Complete Zcmp frame lowering and optimizationRichard-Qin-X2026-08-282-1/+8
* [CodeGen] Add target machine registryRichard-Qin-X2026-08-2810-38/+254
* [CodeGen] Separate assembly emission ownershipRichard-Qin-X2026-08-284-71/+80
* [CodeGen] Separate pass instrumentation ownershipRichard-Qin-X2026-08-283-136/+238
* [CodeGen] Remove pass instrumentation snapshotsRichard-Qin-X2026-08-281-14/+1
* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-282-1/+3
* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-272-1/+3
* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-271-6/+0
* [CodeGen] Remove machine action replayRichard-Qin-X2026-08-271-42/+0
* [CodeGen] Run machine optimizations onceRichard-Qin-X2026-08-272-2/+4
* [CodeGen] Run scheduling transformations onceRichard-Qin-X2026-08-262-2/+3
* [CodeGen] Remove transactional register allocationRichard-Qin-X2026-08-261-5/+5
* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-262-2/+4
* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-263-3/+6
* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-261-4/+6
* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-262-0/+38
* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-263-0/+91
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-252-5/+16
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-252-0/+7
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-253-0/+120
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-251-0/+1
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-242-0/+35
* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-241-0/+3
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-244-5/+16
* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-242-46/+6
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-241-1/+13
* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-242-0/+35
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-221-0/+15
* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-223-0/+19
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-2211-8/+154
* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-191-27/+0
* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-192-39/+1
* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-191-1/+0
* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-193-16/+0
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-193-0/+109
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-1911-3/+53
* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-192-0/+8
* [RISCV][GlobalISel] Match floating comparisonsRichard-Qin-X2026-08-192-0/+8
* [RISCV][GlobalISel] Generate indirect branch selectionRichard-Qin-X2026-08-191-0/+1
* [RISCV][GlobalISel] Generate conditional branch selectionRichard-Qin-X2026-08-172-0/+2
* [RISCV][GlobalISel] Generate integer extension selectionsRichard-Qin-X2026-08-173-7/+27
* [RISCV][GlobalISel] Generate shift selectionsRichard-Qin-X2026-08-163-3/+46
* [RISCV][GlobalISel] Generate integer comparisonsRichard-Qin-X2026-08-163-6/+58
* [RISCV][GlobalISel] Select comparisons against zeroRichard-Qin-X2026-08-162-0/+28
* tablegen: Generate GlobalISel match tablesRichard-Qin-X2026-08-163-2/+110
* [GlobalISel] Propagate no-fp-except flagsRichard-Qin-X2026-08-161-0/+10
* [GlobalISel] Lower inline memory copiesRichard-Qin-X2026-08-151-0/+1
* [GlobalISel] Legalize scalar memory operationsRichard-Qin-X2026-08-151-0/+6
* [GlobalISel] Legalize saturating arithmeticRichard-Qin-X2026-08-151-0/+3
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 14:44:53 +0000