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path: root/backend/lib/CodeGen/CMakeLists.txt
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* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-0/+1
* [CodeGen] Derive quality inputs from source listRichard-Qin-X2026-08-131-163/+12
* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-131-5/+1
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-4/+7
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-131-5/+24
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-131-4/+8
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-121-5/+3
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-121-1/+4
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-121-0/+4
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-111-0/+1
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-091-0/+4
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-0/+105
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-091-0/+7
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-091-0/+40
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-091-0/+4
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+4
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-081-0/+5
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-071-0/+16
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-071-0/+4
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-031-0/+4
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-031-0/+4
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-021-0/+4
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-021-0/+4
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-011-0/+4
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-011-0/+8
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-011-0/+4
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-011-0/+8
* [CodeGen] Add target state and compilation statusRichard-Qin-X2026-08-011-0/+8
* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-011-0/+12
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-011-0/+4
* [CodeGen] Add explicit MachineFunction cloningRichard-Qin-X2026-08-011-0/+4
* [CodeGen] Add strict MachineIR verificationRichard-Qin-X2026-08-011-0/+4
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-011-0/+4
* [CodeGen] Add machine instruction descriptorsRichard-Qin-X2026-08-011-0/+4
* [CodeGen] Build the core MachineIR object modelRichard-Qin-X2026-08-011-0/+24
* [CodeGen] Add machine IR value semanticsRichard-Qin-X2026-08-011-0/+12
* [CodeGen] Add core machine type primitivesRichard-Qin-X2026-08-011-0/+55
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 19:10:04 +0000