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A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.
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backend
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CodeGen
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CMakeLists.txt
Commit message (
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)
Author
Age
Files
Lines
*
[CodeGen] Align pass manager ownership
Richard-Qin-X
2026-08-13
1
-4
/
+7
*
[CodeGen] Split machine liveness components
Richard-Qin-X
2026-08-13
1
-5
/
+24
*
[CodeGen] Split PHI elimination and two-address rewriting
Richard-Qin-X
2026-08-13
1
-4
/
+8
*
[GlobalISel] Split the generic pipeline components
Richard-Qin-X
2026-08-12
1
-5
/
+3
*
[CodeGen] Add TargetInstrInfo ownership
Richard-Qin-X
2026-08-12
1
-1
/
+4
*
[Tooling] Complete the LLVM MIR command-line contract
Richard-Qin-X
2026-08-12
1
-0
/
+4
*
[MIR] Accept fixed-baseline LLVM syntax
Richard-Qin-X
2026-08-11
1
-0
/
+1
*
[MC] Implement RV64GC assembly emission
Richard-Qin-X
2026-08-09
1
-0
/
+4
*
[CodeGen] Implement machine optimization and scheduling
Richard-Qin-X
2026-08-09
1
-0
/
+105
*
[CodeGen] Implement RV64GC frame lowering
Richard-Qin-X
2026-08-09
1
-0
/
+7
*
[CodeGen] Complete register allocation infrastructure
Richard-Qin-X
2026-08-09
1
-0
/
+40
*
[CodeGen] Implement machine liveness analysis
Richard-Qin-X
2026-08-09
1
-0
/
+4
*
[CodeGen] Implement machine SSA exit
Richard-Qin-X
2026-08-08
1
-0
/
+4
*
[CodeGen] Implement RV64GC legalization and instruction selection
Richard-Qin-X
2026-08-08
1
-0
/
+5
*
[CodeGen] Complete machine pass and ABI lowering infrastructure
Richard-Qin-X
2026-08-07
1
-0
/
+16
*
[MIR] Complete document parsing and printing
Richard-Qin-X
2026-08-07
1
-0
/
+4
*
[CodeGen] Add target MIR text schema
Richard-Qin-X
2026-08-03
1
-0
/
+4
*
[CodeGen] Model complete MIR operands
Richard-Qin-X
2026-08-03
1
-0
/
+4
*
[CodeGen] Model machine debug metadata
Richard-Qin-X
2026-08-02
1
-0
/
+4
*
[CodeGen] Add machine metadata graphs
Richard-Qin-X
2026-08-02
1
-0
/
+4
*
[CodeGen] Add machine function records
Richard-Qin-X
2026-08-01
1
-0
/
+4
*
[CodeGen] Add MIR function and block attributes
Richard-Qin-X
2026-08-01
1
-0
/
+8
*
[MIR] Add compilation unit reference context
Richard-Qin-X
2026-08-01
1
-0
/
+4
*
[CodeGen] Add target register descriptions
Richard-Qin-X
2026-08-01
1
-0
/
+8
*
[CodeGen] Add target state and compilation status
Richard-Qin-X
2026-08-01
1
-0
/
+8
*
[CodeGen] Add constant and jump table state
Richard-Qin-X
2026-08-01
1
-0
/
+12
*
[CodeGen] Add MachineFrameInfo
Richard-Qin-X
2026-08-01
1
-0
/
+4
*
[CodeGen] Add explicit MachineFunction cloning
Richard-Qin-X
2026-08-01
1
-0
/
+4
*
[CodeGen] Add strict MachineIR verification
Richard-Qin-X
2026-08-01
1
-0
/
+4
*
[CodeGen] Add transactional MachineIR builder
Richard-Qin-X
2026-08-01
1
-0
/
+4
*
[CodeGen] Add machine instruction descriptors
Richard-Qin-X
2026-08-01
1
-0
/
+4
*
[CodeGen] Build the core MachineIR object model
Richard-Qin-X
2026-08-01
1
-0
/
+24
*
[CodeGen] Add machine IR value semantics
Richard-Qin-X
2026-08-01
1
-0
/
+12
*
[CodeGen] Add core machine type primitives
Richard-Qin-X
2026-08-01
1
-0
/
+55