| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [GlobalISel] Bind register bank optionals once | Richard-Qin-X | 2026-08-29 | 1 | -6/+9 |
| * | [CodeGen] Centralize machine instruction erasure | Richard-Qin-X | 2026-08-28 | 1 | -2/+2 |
| * | [CodeGen] Centralize machine pass property validation | Richard-Qin-X | 2026-08-26 | 1 | -15/+0 |
| * | [RISCV][GlobalISel] Legalize floating-point remainder | Richard-Qin-X | 2026-08-15 | 1 | -0/+6 |
| * | [RISCV] Match LLVM register bank mappings | Richard-Qin-X | 2026-08-13 | 1 | -36/+210 |
| * | [Support] Centralize error context handling | Richard-Qin-X | 2026-08-13 | 1 | -15/+12 |
| * | [CodeGen] Align pass manager ownership | Richard-Qin-X | 2026-08-13 | 1 | -1/+1 |
| * | [CodeGen] Split machine liveness components | Richard-Qin-X | 2026-08-13 | 1 | -1/+1 |
| * | [GlobalISel] Split the generic pipeline components | Richard-Qin-X | 2026-08-12 | 1 | -0/+238 |
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