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path: root/backend/lib/CodeGen/InstructionDescriptor.cpp
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* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-141-0/+13
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* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-11/+13
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-4/+3
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* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-111-2/+6
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-1/+1
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* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-3/+5
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* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-40/+175
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* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-011-8/+0
| | | | Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-011-66/+157
| | | | Validate insertion cursors, operand ownership, descriptor constraints, ties, implicit registers, and memory operands before allocating or publishing an instruction. Share instruction legality checks with the verifier path and preserve deterministic insertion order.
* [CodeGen] Add machine instruction descriptorsRichard-Qin-X2026-08-011-0/+531
Introduce an immutable instruction registry with exact operand, implicit register, tie, pseudo lifecycle, and memory constraints. Validate descriptor tables before publication and use the same rules to verify MachineInstr instances.