| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Centralize machine instruction erasure | Richard-Qin-X | 2026-08-28 | 1 | -4/+3 |
| * | [CodeGen] Run machine optimizations once | Richard-Qin-X | 2026-08-27 | 1 | -24/+4 |
| * | [CodeGen] Centralize machine pass property validation | Richard-Qin-X | 2026-08-26 | 1 | -4/+0 |
| * | [CodeGen] Implement the greedy register allocator pipeline | Richard-Qin-X | 2026-08-25 | 1 | -1/+39 |
| * | [CodeGen] Match LLVM machine copy propagation | Richard-Qin-X | 2026-08-13 | 1 | -133/+107 |
| * | [Support] Centralize error context handling | Richard-Qin-X | 2026-08-13 | 1 | -7/+2 |
| * | [CodeGen] Align pass manager ownership | Richard-Qin-X | 2026-08-13 | 1 | -3/+3 |
| * | [CodeGen] Split machine liveness components | Richard-Qin-X | 2026-08-13 | 1 | -1/+1 |
| * | [RISCV] Consolidate instruction behavior in RISCVInstrInfo | Richard-Qin-X | 2026-08-12 | 1 | -3/+3 |
| * | [Tooling] Complete backend tooling and validation | Richard-Qin-X | 2026-08-10 | 1 | -4/+17 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+362 |
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