aboutsummaryrefslogtreecommitdiff
path: root/backend/lib/CodeGen/MachineIRBuilder.cpp
Commit message (Expand)AuthorAgeFilesLines
* [RISCV][GlobalISel] Legalize scalar bit count operationsRichard-Qin-X2026-08-151-0/+5
* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-108/+130
* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-141-0/+5
* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-141-21/+141
* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-141-0/+193
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-131-4/+2
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-071-0/+13
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-031-0/+75
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-021-4/+30
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-011-18/+21
* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-011-1/+37
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-011-0/+22
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-011-0/+537
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 08:35:32 +0000