| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Generate RISC-V macro fusion rules | Richard-Qin-X | 2026-08-22 | 1 | -2/+4 |
| * | [CodeGen] Remove RCC fallthrough normalization | Richard-Qin-X | 2026-08-19 | 1 | -4/+0 |
| * | [CodeGen] Unify LLVM branch folding pipeline | Richard-Qin-X | 2026-08-19 | 1 | -16/+12 |
| * | [CodeGen] Remove non-LLVM machine DCE placements | Richard-Qin-X | 2026-08-19 | 1 | -6/+0 |
| * | [CodeGen] Remove unsupported post-frame combiner | Richard-Qin-X | 2026-08-19 | 1 | -4/+0 |
| * | [CodeGen] Remove unsupported pre-PEI pseudo expansion | Richard-Qin-X | 2026-08-19 | 1 | -3/+0 |
| * | [CodeGen] Match LLVM machine copy propagation | Richard-Qin-X | 2026-08-13 | 1 | -9/+8 |
| * | [CodeGen] Align pass manager ownership | Richard-Qin-X | 2026-08-13 | 1 | -5/+5 |
| * | [CodeGen] Split machine liveness components | Richard-Qin-X | 2026-08-13 | 1 | -1/+1 |
| * | [RISCV] Consolidate instruction behavior in RISCVInstrInfo | Richard-Qin-X | 2026-08-12 | 1 | -9/+9 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+156 |
