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path: root/backend/lib/CodeGen/MachineOptimizationPipeline.cpp
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* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-241-1/+2
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* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-241-10/+1
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* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-241-1/+8
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* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-221-2/+4
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* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-191-4/+0
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* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-191-16/+12
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* [CodeGen] Remove non-LLVM machine DCE placementsRichard-Qin-X2026-08-191-6/+0
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* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-191-4/+0
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* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-191-3/+0
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* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-131-9/+8
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-5/+5
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* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-131-1/+1
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* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-121-9/+9
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-0/+156
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 08:24:27 +0000