rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[MIR] Omit predictable successors in simplified output	Richard-Qin-X	2026-08-13	2	-24/+69
\|
*	[CodeGen] Preserve LLT annotations on generic opcodes	Richard-Qin-X	2026-08-13	1	-2/+3
\|
*	[CodeGen] Derive quality inputs from source list	Richard-Qin-X	2026-08-13	1	-163/+12
\|
*	[MIR] Qualify pointer iterators	Richard-Qin-X	2026-08-13	1	-3/+3
\|
*	[CodeGen] Reuse register diagnostic formatting	Richard-Qin-X	2026-08-13	1	-2/+1
\|
*	[Support] Centralize error context handling	Richard-Qin-X	2026-08-13	28	-234/+112
\|
*	[CodeGen] Remove the unused property query	Richard-Qin-X	2026-08-13	1	-4/+0
\|
*	[IR] Split LL parsing, assembly writing, and data layout	Richard-Qin-X	2026-08-13	6	-903/+40
\|
*	[Support] Split APInt and APFloat ownership	Richard-Qin-X	2026-08-13	7	-296/+22
\|
*	[CodeGen] Align MIR parser and printer ownership	Richard-Qin-X	2026-08-13	6	-0/+10539
\|
*	[CodeGen] Align pass manager ownership	Richard-Qin-X	2026-08-13	39	-659/+268
\|
*	[CodeGen] Split machine liveness components	Richard-Qin-X	2026-08-13	38	-1195/+1310
\|
*	[CodeGen] Split PHI elimination and two-address rewriting	Richard-Qin-X	2026-08-13	3	-484/+630
\|
*	[RISCV] Split the GlobalISel target components	Richard-Qin-X	2026-08-12	3	-7/+5
\|
*	[GlobalISel] Split the generic pipeline components	Richard-Qin-X	2026-08-12	6	-747/+948
\|
*	[RISCV] Consolidate instruction behavior in RISCVInstrInfo	Richard-Qin-X	2026-08-12	7	-29/+26
\|
*	[CodeGen] Add TargetInstrInfo ownership	Richard-Qin-X	2026-08-12	9	-21/+33
\|
*	[Tooling] Complete the LLVM MIR command-line contract	Richard-Qin-X	2026-08-12	6	-5/+242
\|
*	[Tooling] Adopt LLVM MIR command-line spellings	Richard-Qin-X	2026-08-12	2	-11/+25
\|
*	[CodeGen] Verify local physical live-ins	Richard-Qin-X	2026-08-12	1	-3/+73
\|
*	[CodeGen] Allow dynamic implicit operands on copies	Richard-Qin-X	2026-08-12	1	-1/+1
\|
*	[MIR] Remove alternate layout and float APIs	Richard-Qin-X	2026-08-12	1	-1/+0
\|
*	[CodeGen] Allow narrow atomic RMW memory types	Richard-Qin-X	2026-08-12	1	-1/+1
\|
*	[CodeGen] Preserve variable-sized stack object offsets	Richard-Qin-X	2026-08-12	1	-6/+2
\|
*	[RISCV] Legalize G_VAARG	Richard-Qin-X	2026-08-12	1	-22/+4
\|
*	[RISCV] Legalize llvm.va_copy	Richard-Qin-X	2026-08-12	1	-0/+1
\|
*	[CodeGen] Track reserved register defs precisely	Richard-Qin-X	2026-08-12	2	-9/+8
\|
*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	1	-1/+10
\|
*	[CodeGen] Accept pointer comparisons in G_ICMP	Richard-Qin-X	2026-08-12	1	-4/+12
\|
*	[CodeGen] Treat reserved registers as always live	Richard-Qin-X	2026-08-11	1	-0/+11
\|
*	[CodeGen] Accept conservative physical live-ins	Richard-Qin-X	2026-08-11	1	-2/+2
\|
*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	1	-10/+9
\|
*	[CodeGen] Revisit instructions invalidated by legalization	Richard-Qin-X	2026-08-11	1	-12/+11
\|
*	[RISCV] Legalize narrow atomic compare exchange	Richard-Qin-X	2026-08-11	1	-2/+2
\|
*	[MIR] Parse one-ordering compare-exchange MMOs	Richard-Qin-X	2026-08-11	1	-3/+4
\|
*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	2	-26/+76
\|
*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	10	-73/+165
\|
*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	22	-124/+573
\|
*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	3	-4/+14
\|
*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	4	-0/+371
\|
*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	32	-1/+8164
\|
*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	12	-7/+551
\|
*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	22	-78/+2575
\|
*	[CodeGen] Implement machine liveness analysis	Richard-Qin-X	2026-08-09	6	-32/+1931
\|
*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	8	-49/+1597
\|
*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	2	-0/+619
\|
*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	6	-0/+4100
\|
*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	1	-40/+175
\|
*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	2	-7/+40
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[MIR] Complete document parsing and printing	Richard-Qin-X	2026-08-07	11	-24/+1449
\| \| \| \|	Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.