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A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.
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CodeGen
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Author
Age
Files
Lines
*
[GlobalISel] Legalize G_ABDS and G_ABDU
Richard-Qin-X
2026-08-14
1
-0
/
+149
|
*
[GlobalISel] Legalize G_ABS
Richard-Qin-X
2026-08-14
6
-10
/
+221
|
*
[RISCV] Legalize va_copy intrinsics
Richard-Qin-X
2026-08-14
1
-0
/
+33
|
*
[MIR] Normalize explicit successor probabilities
Richard-Qin-X
2026-08-14
2
-2
/
+37
|
*
[GlobalISel] Match LLVM legalization value tracking
Richard-Qin-X
2026-08-14
8
-36
/
+2045
|
*
[CodeGen] Match LLVM Legalizer ownership
Richard-Qin-X
2026-08-14
10
-131
/
+1630
|
*
[CodeGen] Unify scalar low-level types
Richard-Qin-X
2026-08-13
12
-329
/
+193
|
*
[CodeGen] Match LLVM machine copy propagation
Richard-Qin-X
2026-08-13
3
-142
/
+135
|
*
[CodeGen] Match LLVM branch relaxation semantics
Richard-Qin-X
2026-08-13
1
-12
/
+4
|
*
[RISCV] Match LLVM register bank mappings
Richard-Qin-X
2026-08-13
2
-36
/
+214
|
*
[MIR] Omit predictable successors in simplified output
Richard-Qin-X
2026-08-13
2
-24
/
+69
|
*
[CodeGen] Preserve LLT annotations on generic opcodes
Richard-Qin-X
2026-08-13
1
-2
/
+3
|
*
[CodeGen] Derive quality inputs from source list
Richard-Qin-X
2026-08-13
1
-163
/
+12
|
*
[MIR] Qualify pointer iterators
Richard-Qin-X
2026-08-13
1
-3
/
+3
|
*
[CodeGen] Reuse register diagnostic formatting
Richard-Qin-X
2026-08-13
1
-2
/
+1
|
*
[Support] Centralize error context handling
Richard-Qin-X
2026-08-13
28
-234
/
+112
|
*
[CodeGen] Remove the unused property query
Richard-Qin-X
2026-08-13
1
-4
/
+0
|
*
[IR] Split LL parsing, assembly writing, and data layout
Richard-Qin-X
2026-08-13
6
-903
/
+40
|
*
[Support] Split APInt and APFloat ownership
Richard-Qin-X
2026-08-13
7
-296
/
+22
|
*
[CodeGen] Align MIR parser and printer ownership
Richard-Qin-X
2026-08-13
6
-0
/
+10539
|
*
[CodeGen] Align pass manager ownership
Richard-Qin-X
2026-08-13
39
-659
/
+268
|
*
[CodeGen] Split machine liveness components
Richard-Qin-X
2026-08-13
38
-1195
/
+1310
|
*
[CodeGen] Split PHI elimination and two-address rewriting
Richard-Qin-X
2026-08-13
3
-484
/
+630
|
*
[RISCV] Split the GlobalISel target components
Richard-Qin-X
2026-08-12
3
-7
/
+5
|
*
[GlobalISel] Split the generic pipeline components
Richard-Qin-X
2026-08-12
6
-747
/
+948
|
*
[RISCV] Consolidate instruction behavior in RISCVInstrInfo
Richard-Qin-X
2026-08-12
7
-29
/
+26
|
*
[CodeGen] Add TargetInstrInfo ownership
Richard-Qin-X
2026-08-12
9
-21
/
+33
|
*
[Tooling] Complete the LLVM MIR command-line contract
Richard-Qin-X
2026-08-12
6
-5
/
+242
|
*
[Tooling] Adopt LLVM MIR command-line spellings
Richard-Qin-X
2026-08-12
2
-11
/
+25
|
*
[CodeGen] Verify local physical live-ins
Richard-Qin-X
2026-08-12
1
-3
/
+73
|
*
[CodeGen] Allow dynamic implicit operands on copies
Richard-Qin-X
2026-08-12
1
-1
/
+1
|
*
[MIR] Remove alternate layout and float APIs
Richard-Qin-X
2026-08-12
1
-1
/
+0
|
*
[CodeGen] Allow narrow atomic RMW memory types
Richard-Qin-X
2026-08-12
1
-1
/
+1
|
*
[CodeGen] Preserve variable-sized stack object offsets
Richard-Qin-X
2026-08-12
1
-6
/
+2
|
*
[RISCV] Legalize G_VAARG
Richard-Qin-X
2026-08-12
1
-22
/
+4
|
*
[RISCV] Legalize llvm.va_copy
Richard-Qin-X
2026-08-12
1
-0
/
+1
|
*
[CodeGen] Track reserved register defs precisely
Richard-Qin-X
2026-08-12
2
-9
/
+8
|
*
[RISCV] Model FFLAGS accesses
Richard-Qin-X
2026-08-12
1
-1
/
+10
|
*
[CodeGen] Accept pointer comparisons in G_ICMP
Richard-Qin-X
2026-08-12
1
-4
/
+12
|
*
[CodeGen] Treat reserved registers as always live
Richard-Qin-X
2026-08-11
1
-0
/
+11
|
*
[CodeGen] Accept conservative physical live-ins
Richard-Qin-X
2026-08-11
1
-2
/
+2
|
*
[CodeGen] Remove redundant numeric call-site IDs
Richard-Qin-X
2026-08-11
1
-10
/
+9
|
*
[CodeGen] Revisit instructions invalidated by legalization
Richard-Qin-X
2026-08-11
1
-12
/
+11
|
*
[RISCV] Legalize narrow atomic compare exchange
Richard-Qin-X
2026-08-11
1
-2
/
+2
|
*
[MIR] Parse one-ordering compare-exchange MMOs
Richard-Qin-X
2026-08-11
1
-3
/
+4
|
*
[RISCV] Legalize fixed-baseline RV64 MachineIR
Richard-Qin-X
2026-08-11
2
-26
/
+76
|
*
[MIR] Accept fixed-baseline LLVM syntax
Richard-Qin-X
2026-08-11
10
-73
/
+165
|
*
[Tooling] Complete backend tooling and validation
Richard-Qin-X
2026-08-10
22
-124
/
+573
|
*
[MC] Implement RV64GC object emission
Richard-Qin-X
2026-08-09
3
-4
/
+14
|
*
[MC] Implement RV64GC assembly emission
Richard-Qin-X
2026-08-09
4
-0
/
+371
|
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