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Commit message (Collapse)AuthorAgeFilesLines
* [CodeGen] Separate pass instrumentation ownershipRichard-Qin-X2026-08-283-476/+409
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* [CodeGen] Remove pass instrumentation snapshotsRichard-Qin-X2026-08-281-90/+10
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* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-2818-346/+107
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* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-271-41/+60
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* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-271-3/+0
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* [CodeGen] Remove machine action replayRichard-Qin-X2026-08-273-158/+14
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* [CodeGen] Run machine optimizations onceRichard-Qin-X2026-08-2711-215/+17
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* [CodeGen] Run scheduling transformations onceRichard-Qin-X2026-08-265-136/+27
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* [CodeGen] Remove transactional register allocationRichard-Qin-X2026-08-268-169/+42
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* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-262-55/+18
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* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-263-75/+14
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* [CodeGen] Centralize machine pass property validationRichard-Qin-X2026-08-2624-169/+0
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* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-262-5/+11
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* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-262-0/+103
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* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-264-41/+367
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* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-2512-40/+425
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* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-253-0/+9
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* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-253-3/+621
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* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-242-0/+432
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* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-242-9/+13
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* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-244-11/+8
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* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-243-240/+146
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* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-244-51/+3
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* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-243-1/+104
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* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-224-1/+54
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* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-228-38/+347
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* [CodeGen] Match LLVM final verifier contractRichard-Qin-X2026-08-191-2/+2
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* [CodeGen] Match LLVM finalization contractRichard-Qin-X2026-08-191-2/+2
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* [CodeGen] Match LLVM late pseudo contractRichard-Qin-X2026-08-191-2/+2
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* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-193-169/+0
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* [CodeGen] Match LLVM block placement contractRichard-Qin-X2026-08-191-6/+2
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* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-194-424/+304
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* [CodeGen] Match LLVM tail duplication contractRichard-Qin-X2026-08-191-9/+1
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* [CodeGen] Match LLVM post-machine scheduler contractRichard-Qin-X2026-08-191-7/+1
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* [CodeGen] Match LLVM post-RA pseudo expansion contractRichard-Qin-X2026-08-191-7/+1
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* [CodeGen] Remove non-LLVM machine DCE placementsRichard-Qin-X2026-08-191-6/+0
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* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-192-22/+0
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* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-192-39/+2
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* [CodeGen] Match LLVM shrink wrapping contractRichard-Qin-X2026-08-191-7/+1
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* [CodeGen] Match LLVM post-RA sink contractRichard-Qin-X2026-08-191-3/+1
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* [CodeGen] Match LLVM post-RA LICM contractRichard-Qin-X2026-08-191-3/+1
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* [CodeGen] Match LLVM post-RA combiner contractRichard-Qin-X2026-08-191-1/+1
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* [CodeGen] Match LLVM stack slot coloring contractRichard-Qin-X2026-08-191-6/+1
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* [CodeGen] Match LLVM PBQP allocator input contractRichard-Qin-X2026-08-191-4/+2
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* [CodeGen] Match LLVM machine scheduler contractRichard-Qin-X2026-08-191-6/+1
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* [CodeGen] Match LLVM machine sink input contractRichard-Qin-X2026-08-191-2/+2
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* [CodeGen] Match LLVM prologepilog input contractRichard-Qin-X2026-08-191-2/+1
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* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-193-3/+329
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* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-194-5/+50
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* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-191-0/+28
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generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 21:34:05 +0000