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* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-136-903/+40
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* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-137-296/+22
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* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-136-0/+10539
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1339-659/+268
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* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-1338-1195/+1310
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* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-133-484/+630
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-123-7/+5
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* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-126-747/+948
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* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-127-29/+26
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* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-129-21/+33
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* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-126-5/+242
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* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-122-11/+25
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* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-121-3/+73
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* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-121-1/+1
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* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-121-1/+0
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* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-121-1/+1
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* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-121-6/+2
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* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-22/+4
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* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+1
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* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-122-9/+8
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* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-121-1/+10
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* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-4/+12
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* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+11
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* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-2/+2
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* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-10/+9
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* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-12/+11
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* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-2/+2
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* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-111-3/+4
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* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-112-26/+76
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* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1110-73/+165
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* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1022-124/+573
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* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-093-4/+14
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* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-094-0/+371
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0932-1/+8164
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* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-0912-7/+551
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* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0922-78/+2575
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* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-096-32/+1931
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* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-088-49/+1597
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* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+619
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* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-076-0/+4100
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* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-40/+175
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* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-072-7/+40
| | | | Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-0711-24/+1449
| | | | Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-044-1/+200
| | | | Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-038-21/+643
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* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-038-1/+600
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* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-0210-11/+285
| | | | Replace marker-based metadata operands with scoped references and inline DIExpression values. Add structured DILocation chains, instruction debug attachments, stack variable records, and entry values with unified verification, builder support, and deterministic cloning.
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-024-0/+125
| | | | Model ordered function-local metadata tuples with explicit embedded-IR and MachineFunction reference scopes. Preserve slot zero, distinct nodes, forward references, and cyclic graphs while verifying function-local closure and cloning the graph deterministically.
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-015-0/+143
| | | | Add monotonic MIR debug instruction numbers and structured value substitutions. Verify live number uniqueness, meta-instruction exclusion, substitution graph integrity, and target subregister references while preserving debug identities during cloning.
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-014-0/+263
| | | | Represent callee-saved registers, call-site information, called globals, and prefetch targets in the core MachineIR model. Verify target and instruction references and remap StableIDs during explicit function cloning.
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 19:08:42 +0000