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* [MIR] Print target generic operand typesRichard-Qin-X2026-08-151-2/+2
| | | | Use the instruction descriptor's Generic flag when deduplicating LLT annotations so target-specific generic pseudos follow LLVM MIR spelling.
* [GlobalISel] Narrow scalar selectsRichard-Qin-X2026-08-151-10/+86
| | | | Match LLVM's narrowScalarSelect lowering for wide scalar values. Build widened sources from LLT destinations so CSE hits reuse the actual result register instead of introducing copies.
* [GlobalISel] Narrow scalar bitwise operationsRichard-Qin-X2026-08-151-0/+78
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* [GlobalISel] Legalize constants and implicit definitionsRichard-Qin-X2026-08-151-0/+139
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* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-158-244/+1187
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* [GlobalISel] Legalize G_ABDS and G_ABDURichard-Qin-X2026-08-141-0/+149
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* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-146-10/+221
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* [RISCV] Legalize va_copy intrinsicsRichard-Qin-X2026-08-141-0/+33
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* [MIR] Normalize explicit successor probabilitiesRichard-Qin-X2026-08-142-2/+37
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* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-148-36/+2045
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* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-1410-131/+1630
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* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-1312-329/+193
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* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-133-142/+135
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* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-131-12/+4
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* [RISCV] Match LLVM register bank mappingsRichard-Qin-X2026-08-132-36/+214
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* [MIR] Omit predictable successors in simplified outputRichard-Qin-X2026-08-132-24/+69
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* [CodeGen] Preserve LLT annotations on generic opcodesRichard-Qin-X2026-08-131-2/+3
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* [CodeGen] Derive quality inputs from source listRichard-Qin-X2026-08-131-163/+12
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* [MIR] Qualify pointer iteratorsRichard-Qin-X2026-08-131-3/+3
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* [CodeGen] Reuse register diagnostic formattingRichard-Qin-X2026-08-131-2/+1
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* [Support] Centralize error context handlingRichard-Qin-X2026-08-1328-234/+112
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* [CodeGen] Remove the unused property queryRichard-Qin-X2026-08-131-4/+0
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* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-136-903/+40
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* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-137-296/+22
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* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-136-0/+10539
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1339-659/+268
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* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-1338-1195/+1310
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* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-133-484/+630
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-123-7/+5
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* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-126-747/+948
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* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-127-29/+26
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* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-129-21/+33
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* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-126-5/+242
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* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-122-11/+25
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* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-121-3/+73
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* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-121-1/+1
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* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-121-1/+0
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* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-121-1/+1
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* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-121-6/+2
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* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-22/+4
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* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+1
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* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-122-9/+8
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* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-121-1/+10
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* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-4/+12
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* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+11
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* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-2/+2
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* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-10/+9
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* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-12/+11
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* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-2/+2
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* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-111-3/+4
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