| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Implement make-compressible pass | Richard-Qin-X | 2026-08-25 | 1 | -0/+39 |
| * | [CodeGen] Implement RISC-V machine outlining | Richard-Qin-X | 2026-08-25 | 1 | -0/+17 |
| * | [RISCV][GlobalISel] Select and expand global addresses | Richard-Qin-X | 2026-08-19 | 1 | -0/+27 |
| * | [RISCV] Split the GlobalISel target components | Richard-Qin-X | 2026-08-12 | 1 | -2/+2 |
| * | [MIR] Accept fixed-baseline LLVM syntax | Richard-Qin-X | 2026-08-11 | 1 | -1/+120 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -13/+11 |
| * | [MIR] Complete document parsing and printing | Richard-Qin-X | 2026-08-07 | 1 | -40/+148 |
| * | [MIR] Add compilation unit reference context | Richard-Qin-X | 2026-08-01 | 1 | -0/+636 |
