| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Support] Centralize error context handling | Richard-Qin-X | 2026-08-13 | 1 | -0/+5 |
| * | [Support] Split APInt and APFloat ownership | Richard-Qin-X | 2026-08-13 | 3 | -1/+1738 |
| * | [RISCV] Split the GlobalISel target components | Richard-Qin-X | 2026-08-12 | 1 | -3/+3 |
| * | [MIR] Accept fixed-baseline LLVM syntax | Richard-Qin-X | 2026-08-11 | 2 | -10/+37 |
| * | [Tooling] Complete backend tooling and validation | Richard-Qin-X | 2026-08-10 | 3 | -1/+165 |
| * | [MC] Implement RV64GC object emission | Richard-Qin-X | 2026-08-09 | 1 | -0/+8 |
| * | [MC] Implement RV64GC assembly emission | Richard-Qin-X | 2026-08-09 | 1 | -0/+2 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+10 |
| * | [CodeGen] Implement RV64GC frame lowering | Richard-Qin-X | 2026-08-09 | 1 | -0/+2 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -0/+2 |
| * | [Support] Add MIR YAML parsing infrastructure | Richard-Qin-X | 2026-08-01 | 3 | -2/+1318 |
| * | [Backend] Establish standalone build infrastructure | Richard-Qin-X | 2026-08-01 | 2 | -0/+68 |
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