| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [TableGen] Split the target description generator | Richard-Qin-X | 2026-08-13 | 1 | -3063/+0 |
| * | [RISCV] Model typed floating-point register views | Richard-Qin-X | 2026-08-11 | 1 | -6/+6 |
| * | [MC] Implement RV64GC object emission | Richard-Qin-X | 2026-08-09 | 1 | -9/+21 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -3/+4 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -12/+15 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -6/+1903 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 1 | -0/+1150 |
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