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* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-092-13/+18
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* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-072-6/+1904
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* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-072-0/+1184
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.