rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[TableGen] Split the target description generator	Richard-Qin-X	2026-08-13	2	-3100/+0
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*	[RISCV] Model typed floating-point register views	Richard-Qin-X	2026-08-11	1	-6/+6
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	1	-9/+21
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	1	-3/+4
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	2	-13/+18
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	2	-6/+1904
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	2	-0/+1184
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.