aboutsummaryrefslogtreecommitdiff
path: root/backend
Commit message (Collapse)AuthorAgeFilesLines
* [MIR] Merge identical scalar type branchesRichard-Qin-X2026-08-291-5/+1
|
* [RISCV] Merge identical selector casesRichard-Qin-X2026-08-291-2/+0
|
* [RISCV] Widen jump table entry size arithmeticRichard-Qin-X2026-08-291-1/+1
|
* [RISCV] Reuse validated Zcmp frame offsetsRichard-Qin-X2026-08-291-8/+12
|
* [RISCV] Assert merged memory offset invariantsRichard-Qin-X2026-08-291-0/+2
|
* [RISCV] Reuse validated move registersRichard-Qin-X2026-08-291-5/+9
|
* [GlobalISel] Bind register bank optionals onceRichard-Qin-X2026-08-291-6/+9
|
* [GlobalISel] Assert vector element type invariantsRichard-Qin-X2026-08-291-3/+7
|
* [CodeGen] Bind virtual register types onceRichard-Qin-X2026-08-291-2/+3
|
* [CodeGen] Apply LLVM declaration styleRichard-Qin-X2026-08-293-3/+3
|
* [TableGen] Assert normalized MC pseudo operandsRichard-Qin-X2026-08-291-0/+2
|
* [TableGen] Preserve optional target description valuesRichard-Qin-X2026-08-292-9/+10
|
* [GlobalISel] Remove redundant PHI narrowing checksRichard-Qin-X2026-08-291-12/+7
|
* [CodeGen] Complete LaneMask bitwise operationsRichard-Qin-X2026-08-284-17/+19
|
* [Support] Use standard power-of-two checksRichard-Qin-X2026-08-288-39/+20
|
* [CMake] Remove unused clang-tidy file registrationRichard-Qin-X2026-08-2838-281/+81
|
* [RISCV] Complete Zcmp frame lowering and optimizationRichard-Qin-X2026-08-288-210/+439
|
* [RISCV] Generate complete Zcmp instruction definitionsRichard-Qin-X2026-08-286-44/+217
|
* [CodeGen] Add target machine registryRichard-Qin-X2026-08-2824-233/+735
|
* [CodeGen] Separate assembly emission ownershipRichard-Qin-X2026-08-2815-930/+1033
|
* [RISCV] Separate calling convention assignmentRichard-Qin-X2026-08-286-479/+566
|
* [CodeGen] Separate pass instrumentation ownershipRichard-Qin-X2026-08-287-612/+648
|
* [CodeGen] Remove pass instrumentation snapshotsRichard-Qin-X2026-08-282-104/+11
|
* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-2830-474/+148
|
* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-279-159/+179
|
* [RISCV] Generate atomic RMW selectionRichard-Qin-X2026-08-273-95/+366
|
* [RISCV] Remove unused selector helpersRichard-Qin-X2026-08-271-80/+0
|
* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-273-93/+0
|
* [CodeGen] Remove machine action replayRichard-Qin-X2026-08-275-214/+16
|
* [CodeGen] Run machine optimizations onceRichard-Qin-X2026-08-2713-217/+21
|
* [CodeGen] Run scheduling transformations onceRichard-Qin-X2026-08-267-138/+30
|
* [CodeGen] Remove transactional register allocationRichard-Qin-X2026-08-269-174/+47
|
* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-264-57/+22
|
* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-266-78/+20
|
* [CodeGen] Centralize machine pass property validationRichard-Qin-X2026-08-2624-169/+0
|
* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-2610-27/+318
|
* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-2610-5/+667
|
* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-2610-43/+554
|
* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-264-0/+642
|
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-2516-46/+454
|
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-2511-4/+492
|
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-2510-6/+1167
|
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-254-0/+522
|
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-259-0/+392
|
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-246-1/+478
|
* [RISCV] Implement save and restore libcallsRichard-Qin-X2026-08-243-75/+347
|
* [CodeGen] Match LLVM callee-save live-insRichard-Qin-X2026-08-241-1/+1
|
* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-247-104/+102
|
* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-243-209/+290
|
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-2415-230/+393
|
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-28 23:28:55 +0000