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path: root/backend/lib/Target/RISCV/CMakeLists.txt
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* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-261-0/+3
* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-261-0/+1
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-251-0/+3
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-251-0/+1
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-251-0/+2
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-251-0/+2
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-221-0/+10
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-221-0/+10
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-191-0/+13
* [RISCV][GlobalISel] Generate frame index selectionRichard-Qin-X2026-08-191-0/+1
* [RISCV][GlobalISel] Generate conditional branch selectionRichard-Qin-X2026-08-171-0/+1
* [RISCV][GlobalISel] Generate shift selectionsRichard-Qin-X2026-08-161-0/+1
* [RISCV][GlobalISel] Generate floating-point selectionsRichard-Qin-X2026-08-161-1/+2
* tablegen: Generate GlobalISel match tablesRichard-Qin-X2026-08-161-3/+31
* [TableGen] Split the target description generatorRichard-Qin-X2026-08-131-2/+2
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-8/+16
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-121-4/+7
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-0/+4
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-0/+8
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-101-0/+4
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-091-0/+18
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-091-1/+19
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-0/+18
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-091-0/+3
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-091-0/+3
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-081-0/+4
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-071-0/+4
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-8/+26
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+79
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 09:10:44 +0000