| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Legalize fixed-baseline RV64 MachineIR | Richard-Qin-X | 2026-08-11 | 1 | -0/+8 |
| * | [Tooling] Complete backend tooling and validation | Richard-Qin-X | 2026-08-10 | 1 | -0/+4 |
| * | [MC] Implement RV64GC object emission | Richard-Qin-X | 2026-08-09 | 1 | -0/+18 |
| * | [MC] Implement RV64GC assembly emission | Richard-Qin-X | 2026-08-09 | 1 | -1/+19 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+18 |
| * | [CodeGen] Implement RV64GC frame lowering | Richard-Qin-X | 2026-08-09 | 1 | -0/+3 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -0/+3 |
| * | [CodeGen] Implement RV64GC legalization and instruction selection | Richard-Qin-X | 2026-08-08 | 1 | -0/+4 |
| * | [CodeGen] Complete machine pass and ABI lowering infrastructure | Richard-Qin-X | 2026-08-07 | 1 | -0/+4 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -8/+26 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 1 | -0/+79 |
