rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Accept symbolic low operands in loads and stores	Richard-Qin-X	2026-08-12	1	-15/+15
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*	[RISCV] Allow frame indices in ADDI	Richard-Qin-X	2026-08-12	1	-1/+1
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*	[RISCV] Model dynamic rounding-mode state	Richard-Qin-X	2026-08-12	1	-0/+50
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*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	1	-0/+39
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*	[RISCV] Describe the GPR select pseudo	Richard-Qin-X	2026-08-12	1	-0/+15
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*	[RISCV] Model target-specific generic opcodes	Richard-Qin-X	2026-08-12	1	-0/+163
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*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	1	-3/+5
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*	[RISCV] Model typed floating-point register views	Richard-Qin-X	2026-08-11	1	-43/+75
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*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	1	-0/+19
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*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	1	-4/+0
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*	[RISCV] Match LLVM call-frame pseudo semantics	Richard-Qin-X	2026-08-11	1	-0/+4
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	1	-3/+24
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	1	-0/+195
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	1	-2/+55
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	1	-11/+11
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	1	-1/+2978
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	1	-0/+220
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.