| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Model typed floating-point register views | Richard-Qin-X | 2026-08-11 | 1 | -43/+75 |
| * | [RISCV] Add LP64 calling-convention facts | Richard-Qin-X | 2026-08-11 | 1 | -0/+19 |
| * | [CodeGen] Remove redundant numeric call-site IDs | Richard-Qin-X | 2026-08-11 | 1 | -4/+0 |
| * | [RISCV] Match LLVM call-frame pseudo semantics | Richard-Qin-X | 2026-08-11 | 1 | -0/+4 |
| * | [RISCV] Legalize fixed-baseline RV64 MachineIR | Richard-Qin-X | 2026-08-11 | 1 | -3/+24 |
| * | [MC] Implement RV64GC object emission | Richard-Qin-X | 2026-08-09 | 1 | -0/+195 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -2/+55 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -11/+11 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -1/+2978 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 1 | -0/+220 |
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index : rcc-project | |
| A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser. |
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