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path: root/backend/lib/Target/RISCV/RISCV.rccdesc
Commit message (Collapse)AuthorAgeFilesLines
* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-121-1/+1
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* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-0/+77
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* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-121-0/+237
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* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-121-52/+0
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* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-15/+15
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* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-1/+1
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* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-0/+50
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* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-121-0/+39
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* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
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* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
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* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-121-3/+5
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* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-111-43/+75
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* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-111-0/+19
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* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-4/+0
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* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-111-0/+4
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* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-3/+24
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* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-091-0/+195
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-2/+55
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* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-091-11/+11
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* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-1/+2978
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* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+220
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.