| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Implement save and restore libcalls | Richard-Qin-X | 2026-08-24 | 1 | -11/+33 |
| * | [RISCV] Generate MC pseudo lowering | Richard-Qin-X | 2026-08-22 | 1 | -178/+9 |
| * | [RISCV][GlobalISel] Select and expand global addresses | Richard-Qin-X | 2026-08-19 | 1 | -0/+123 |
| * | [RISCV][GlobalISel] Generate indirect branch selection | Richard-Qin-X | 2026-08-19 | 1 | -0/+47 |
| * | [CodeGen] Unify scalar low-level types | Richard-Qin-X | 2026-08-13 | 1 | -2/+3 |
| * | [RISCV] Remove physical register forwarding helpers | Richard-Qin-X | 2026-08-13 | 1 | -14/+7 |
| * | [RISCV] Use the generated opcode conversion | Richard-Qin-X | 2026-08-13 | 1 | -16/+12 |
| * | [RISCV] Split the GlobalISel target components | Richard-Qin-X | 2026-08-12 | 1 | -1/+1 |
| * | [RISCV] Model FFLAGS accesses | Richard-Qin-X | 2026-08-12 | 1 | -0/+51 |
| * | [CodeGen] Remove redundant numeric call-site IDs | Richard-Qin-X | 2026-08-11 | 1 | -7/+3 |
| * | [RISCV] Legalize fixed-baseline RV64 MachineIR | Richard-Qin-X | 2026-08-11 | 1 | -0/+40 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+512 |
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