| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV][GlobalISel] Generate indirect branch selection | Richard-Qin-X | 2026-08-19 | 1 | -4/+14 |
| * | [GlobalISel] Lower stack operations | Richard-Qin-X | 2026-08-15 | 1 | -1/+8 |
| * | [GlobalISel] Match LLVM legalization value tracking | Richard-Qin-X | 2026-08-14 | 1 | -1/+5 |
| * | [RISCV] Describe vector tuple registers | Richard-Qin-X | 2026-08-12 | 1 | -0/+86 |
| * | [RISCV] Model typed floating-point register views | Richard-Qin-X | 2026-08-11 | 1 | -0/+37 |
| * | [RISCV] Add LP64 calling-convention facts | Richard-Qin-X | 2026-08-11 | 1 | -3/+9 |
| * | [RISCV] Legalize fixed-baseline RV64 MachineIR | Richard-Qin-X | 2026-08-11 | 1 | -0/+4 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -0/+61 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 1 | -0/+103 |
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