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* [CodeGen] Apply LLVM declaration styleRichard-Qin-X2026-08-291-1/+1
* [CMake] Remove unused clang-tidy file registrationRichard-Qin-X2026-08-281-31/+2
* [RISCV] Complete Zcmp frame lowering and optimizationRichard-Qin-X2026-08-284-206/+377
* [RISCV] Generate complete Zcmp instruction definitionsRichard-Qin-X2026-08-286-44/+217
* [CodeGen] Add target machine registryRichard-Qin-X2026-08-284-14/+176
* [CodeGen] Separate assembly emission ownershipRichard-Qin-X2026-08-288-807/+532
* [RISCV] Separate calling convention assignmentRichard-Qin-X2026-08-286-479/+566
* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-2810-127/+38
* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-272-95/+56
* [RISCV] Generate atomic RMW selectionRichard-Qin-X2026-08-273-95/+366
* [RISCV] Remove unused selector helpersRichard-Qin-X2026-08-271-80/+0
* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-271-84/+0
* [CodeGen] Remove machine action replayRichard-Qin-X2026-08-271-14/+2
* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-267-18/+301
* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-265-4/+524
* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-264-0/+642
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-252-1/+13
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-255-4/+437
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-252-0/+345
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-254-0/+522
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-258-0/+391
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-242-1/+11
* [RISCV] Implement save and restore libcallsRichard-Qin-X2026-08-243-75/+347
* [CodeGen] Match LLVM callee-save live-insRichard-Qin-X2026-08-241-1/+1
* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-244-98/+83
* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-241-200/+277
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-245-208/+360
* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-241-57/+27
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-245-95/+121
* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-241-0/+220
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-225-193/+78
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-229-36/+250
* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-191-2/+1
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-195-5/+250
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-1911-7/+359
* [RISCV][GlobalISel] Generate integer store selectionRichard-Qin-X2026-08-192-80/+76
* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-192-74/+254
* [RISCV][GlobalISel] Generate frame index selectionRichard-Qin-X2026-08-192-0/+17
* [RISCV][GlobalISel] Correct floating constant materializationRichard-Qin-X2026-08-191-3/+16
* [RISCV][GlobalISel] Match floating comparisonsRichard-Qin-X2026-08-192-142/+316
* [RISCV][GlobalISel] Generate trap selectionRichard-Qin-X2026-08-193-16/+28
* [RISCV][GlobalISel] Generate select instruction matchingRichard-Qin-X2026-08-195-161/+229
* [RISCV][GlobalISel] Generate indirect branch selectionRichard-Qin-X2026-08-198-21/+106
* [RISCV][GlobalISel] Generate conditional branch selectionRichard-Qin-X2026-08-174-23/+253
* [RISCV][GlobalISel] Generate direct branch selectionRichard-Qin-X2026-08-172-13/+10
* [RISCV][GlobalISel] Generate implicit-def selectionRichard-Qin-X2026-08-172-3/+10
* [RISCV][GlobalISel] Constrain core copies during selectionRichard-Qin-X2026-08-171-0/+15
* [RISCV][GlobalISel] Generate integer extension selectionsRichard-Qin-X2026-08-173-126/+205
* [RISCV][GlobalISel] Remove lowered overflow selectionsRichard-Qin-X2026-08-161-367/+0
* [RISCV][GlobalISel] Remove lowered minmax selectionsRichard-Qin-X2026-08-161-117/+0
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 12:00:26 +0000