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A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.
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RISCV
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Author
Age
Files
Lines
*
[GlobalISel] Propagate no-fp-except flags
Richard-Qin-X
2026-08-16
1
-0
/
+15
|
*
[RISCV][GlobalISel] Select mixed-width copy-sign
Richard-Qin-X
2026-08-16
2
-4
/
+44
|
*
[RISCV][GlobalISel] Select word division pseudos
Richard-Qin-X
2026-08-16
1
-1
/
+10
|
*
[RISCV][GlobalISel] Select RV64 word shifts
Richard-Qin-X
2026-08-16
1
-0
/
+69
|
*
[RISCV][GlobalISel] Select constant operands as immediates
Richard-Qin-X
2026-08-16
1
-23
/
+114
|
*
[RISCV][GlobalISel] Select word shift pseudos
Richard-Qin-X
2026-08-15
1
-2
/
+8
|
*
[RISCV][GlobalISel] Match LLVM constant materialization
Richard-Qin-X
2026-08-15
5
-196
/
+246
|
*
[RISCV][GlobalISel] Constrain selected builder operands
Richard-Qin-X
2026-08-15
1
-1
/
+73
|
*
[GlobalISel] Legalize RISC-V va_start
Richard-Qin-X
2026-08-15
2
-0
/
+87
|
*
[GlobalISel] Legalize RISC-V jump tables
Richard-Qin-X
2026-08-15
2
-0
/
+206
|
*
[GlobalISel] Legalize multiply with overflow
Richard-Qin-X
2026-08-15
1
-0
/
+7
|
*
[RISCV][GlobalISel] Legalize floating-point classes
Richard-Qin-X
2026-08-15
1
-1
/
+67
|
*
[RISCV][GlobalISel] Legalize floating-point remainder
Richard-Qin-X
2026-08-15
3
-17
/
+46
|
*
[RISCV][GlobalISel] Widen integer-to-floating conversions to XLEN
Richard-Qin-X
2026-08-15
1
-0
/
+11
|
*
[RISCV][GlobalISel] Legalize floating-point to integer conversions
Richard-Qin-X
2026-08-15
2
-38
/
+57
|
*
[GlobalISel] Lower floating-point conversion libcalls
Richard-Qin-X
2026-08-15
2
-54
/
+91
|
*
[GlobalISel] Lower stack operations
Richard-Qin-X
2026-08-15
1
-1
/
+8
|
*
[RISCV][GlobalISel] Preserve Zbb sign extensions
Richard-Qin-X
2026-08-15
2
-1
/
+6
|
*
[RISCV][GlobalISel] Legalize scalar bit count operations
Richard-Qin-X
2026-08-15
1
-12
/
+49
|
*
[GlobalISel] Lower byte-swap operations
Richard-Qin-X
2026-08-15
1
-1
/
+5
|
*
[GlobalISel] Use generic compare-exchange legalization
Richard-Qin-X
2026-08-15
1
-295
/
+5
|
*
[GlobalISel] Lower integer operations to libcalls
Richard-Qin-X
2026-08-15
1
-2
/
+9
|
*
[RISCV] Match explicit target feature semantics
Richard-Qin-X
2026-08-15
1
-5
/
+14
|
*
[GlobalISel] Lower integer rotate operations
Richard-Qin-X
2026-08-15
1
-0
/
+28
|
*
[GlobalISel] Legalize constants and implicit definitions
Richard-Qin-X
2026-08-15
1
-34
/
+36
|
*
[GlobalISel] Match LLVM CSE builder result semantics
Richard-Qin-X
2026-08-15
1
-4
/
+5
|
*
[GlobalISel] Legalize G_ABDS and G_ABDU
Richard-Qin-X
2026-08-14
3
-178
/
+19
|
*
[GlobalISel] Legalize G_ABS
Richard-Qin-X
2026-08-14
1
-0
/
+86
|
*
[RISCV] Legalize va_copy intrinsics
Richard-Qin-X
2026-08-14
2
-0
/
+122
|
*
[GlobalISel] Match LLVM legalization value tracking
Richard-Qin-X
2026-08-14
2
-1
/
+69
|
*
[CodeGen] Match LLVM Legalizer ownership
Richard-Qin-X
2026-08-14
3
-3090
/
+410
|
*
[CodeGen] Unify scalar low-level types
Richard-Qin-X
2026-08-13
6
-436
/
+457
|
*
[CodeGen] Match LLVM machine copy propagation
Richard-Qin-X
2026-08-13
2
-6
/
+342
|
*
[CodeGen] Match LLVM branch relaxation semantics
Richard-Qin-X
2026-08-13
2
-1
/
+75
|
*
[RISCV] Model non-ISA subtarget features
Richard-Qin-X
2026-08-13
1
-7
/
+70
|
*
[RISCV] Match LLVM register bank mappings
Richard-Qin-X
2026-08-13
3
-28
/
+266
|
*
[RISCV] Preserve wide carry instruction order
Richard-Qin-X
2026-08-13
1
-10
/
+18
|
*
[RISCV] Centralize legalizer register type queries
Richard-Qin-X
2026-08-13
1
-118
/
+97
|
*
[RISCV] Remove physical register forwarding helpers
Richard-Qin-X
2026-08-13
3
-57
/
+39
|
*
[RISCV] Use the generated opcode conversion
Richard-Qin-X
2026-08-13
8
-194
/
+164
|
*
[TableGen] Split the target description generator
Richard-Qin-X
2026-08-13
1
-2
/
+2
|
*
[IR] Split LL parsing, assembly writing, and data layout
Richard-Qin-X
2026-08-13
1
-175
/
+43
|
*
[Support] Split APInt and APFloat ownership
Richard-Qin-X
2026-08-13
4
-17
/
+15
|
*
[CodeGen] Align pass manager ownership
Richard-Qin-X
2026-08-13
1
-10
/
+12
|
*
[CodeGen] Split PHI elimination and two-address rewriting
Richard-Qin-X
2026-08-13
1
-3
/
+4
|
*
[RISCV] Split the GlobalISel target components
Richard-Qin-X
2026-08-12
22
-6638
/
+6854
|
*
[GlobalISel] Split the generic pipeline components
Richard-Qin-X
2026-08-12
2
-14
/
+16
|
*
[RISCV] Consolidate instruction behavior in RISCVInstrInfo
Richard-Qin-X
2026-08-12
6
-214
/
+140
|
*
[CodeGen] Add TargetInstrInfo ownership
Richard-Qin-X
2026-08-12
1
-2
/
+2
|
*
[Tooling] Remove the duplicate assembly emitter
Richard-Qin-X
2026-08-12
1
-14
/
+0
|
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