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Commit message (Collapse)AuthorAgeFilesLines
* [RISCV][GlobalISel] Preserve Zbb sign extensionsRichard-Qin-X2026-08-152-1/+6
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* [RISCV][GlobalISel] Legalize scalar bit count operationsRichard-Qin-X2026-08-151-12/+49
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* [GlobalISel] Lower byte-swap operationsRichard-Qin-X2026-08-151-1/+5
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* [GlobalISel] Use generic compare-exchange legalizationRichard-Qin-X2026-08-151-295/+5
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* [GlobalISel] Lower integer operations to libcallsRichard-Qin-X2026-08-151-2/+9
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* [RISCV] Match explicit target feature semanticsRichard-Qin-X2026-08-151-5/+14
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* [GlobalISel] Lower integer rotate operationsRichard-Qin-X2026-08-151-0/+28
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* [GlobalISel] Legalize constants and implicit definitionsRichard-Qin-X2026-08-151-34/+36
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* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-4/+5
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* [GlobalISel] Legalize G_ABDS and G_ABDURichard-Qin-X2026-08-143-178/+19
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* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-141-0/+86
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* [RISCV] Legalize va_copy intrinsicsRichard-Qin-X2026-08-142-0/+122
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* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-142-1/+69
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* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-143-3090/+410
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* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-136-436/+457
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* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-132-6/+342
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* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-132-1/+75
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* [RISCV] Model non-ISA subtarget featuresRichard-Qin-X2026-08-131-7/+70
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* [RISCV] Match LLVM register bank mappingsRichard-Qin-X2026-08-133-28/+266
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* [RISCV] Preserve wide carry instruction orderRichard-Qin-X2026-08-131-10/+18
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* [RISCV] Centralize legalizer register type queriesRichard-Qin-X2026-08-131-118/+97
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* [RISCV] Remove physical register forwarding helpersRichard-Qin-X2026-08-133-57/+39
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* [RISCV] Use the generated opcode conversionRichard-Qin-X2026-08-138-194/+164
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* [TableGen] Split the target description generatorRichard-Qin-X2026-08-131-2/+2
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* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-131-175/+43
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* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-134-17/+15
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-10/+12
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* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-131-3/+4
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-1222-6638/+6854
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* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-122-14/+16
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* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-126-214/+140
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* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-121-2/+2
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* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-14/+0
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* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-121-2/+11
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* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-122-1/+87
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* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-0/+77
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* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-123-2/+253
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* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-122-53/+3
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* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+4
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* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-3/+188
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* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-15/+15
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* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+103
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* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-1/+1
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* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-0/+50
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* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-122-0/+90
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* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
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* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
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* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-125-12/+44
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