rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Accept symbolic low operands in loads and stores	Richard-Qin-X	2026-08-12	1	-15/+15
\|
*	[RISCV] Legalize llvm.va_copy	Richard-Qin-X	2026-08-12	1	-0/+103
\|
*	[RISCV] Allow frame indices in ADDI	Richard-Qin-X	2026-08-12	1	-1/+1
\|
*	[RISCV] Model dynamic rounding-mode state	Richard-Qin-X	2026-08-12	1	-0/+50
\|
*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	2	-0/+90
\|
*	[RISCV] Describe the GPR select pseudo	Richard-Qin-X	2026-08-12	1	-0/+15
\|
*	[RISCV] Model target-specific generic opcodes	Richard-Qin-X	2026-08-12	1	-0/+163
\|
*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	5	-12/+44
\|
*	[RISCV] Model typed floating-point register views	Richard-Qin-X	2026-08-11	6	-71/+177
\|
*	[RISCV] Order call operands like LLVM MIR	Richard-Qin-X	2026-08-11	1	-8/+8
\|
*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	4	-55/+97
\|
*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	4	-20/+5
\|
*	[RISCV] Match LLVM call-frame pseudo semantics	Richard-Qin-X	2026-08-11	4	-74/+33
\|
*	[RISCV] Use canonical copies for full ABI values	Richard-Qin-X	2026-08-11	1	-4/+10
\|
*	[RISCV] Lower multiply without M through libcalls	Richard-Qin-X	2026-08-11	1	-3/+123
\|
*	[RISCV] Accept generic scalars in call lowering	Richard-Qin-X	2026-08-11	1	-3/+2
\|
*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	4	-7/+130
\|
*	[RISCV] Fold narrow binary artifact chains	Richard-Qin-X	2026-08-11	1	-15/+49
\|
*	[RISCV] Preserve folded constant placement	Richard-Qin-X	2026-08-11	1	-0/+18
\|
*	[RISCV] Reuse compare operand extensions	Richard-Qin-X	2026-08-11	1	-0/+28
\|
*	[RISCV] Legalize integer compares to RV64 containers	Richard-Qin-X	2026-08-11	1	-4/+151
\|
*	[RISCV] Preserve live constants when folding extensions	Richard-Qin-X	2026-08-11	1	-2/+3
\|
*	[RISCV] Lower cmpxchg with success	Richard-Qin-X	2026-08-11	1	-0/+94
\|
*	[RISCV] Preserve narrow cmpxchg results when widening	Richard-Qin-X	2026-08-11	1	-2/+3
\|
*	[RISCV] Legalize narrow atomic compare exchange	Richard-Qin-X	2026-08-11	1	-0/+140
\|
*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	9	-32/+2824
\|
*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	2	-0/+166
\|
*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	7	-25/+1983
\|
*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	4	-1/+1522
\|
*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	9	-33/+1693
\|
*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	3	-0/+2106
\|
*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	3	-11/+293
\|
*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	1	-0/+199
\|
*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	2	-0/+3243
\|
*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	2	-0/+1477
\|
*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	3	-9/+3065
\|
*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	3	-0/+402
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.