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* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-119-32/+2824
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-102-0/+166
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-097-25/+1983
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-094-1/+1522
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-099-33/+1693
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-093-0/+2106
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-093-11/+293
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+199
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+3243
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-072-0/+1477
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-073-9/+3065
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-073-0/+402
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 21:31:49 +0000