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* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-114-74/+33
* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-111-4/+10
* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-3/+123
* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-3/+2
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-115-17/+147
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-15/+49
* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-12/+11
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-111-3/+5
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-0/+94
* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-2/+3
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-112-2/+142
* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-112-43/+42
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-1111-58/+2900
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1130-623/+1739
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1050-2871/+7754
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0921-45/+4393
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0921-1/+3982
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0943-37/+9871
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-0916-7/+2659
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0935-154/+2955
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-096-32/+1931
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-089-49/+1796
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-084-0/+3862
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-078-0/+5577
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-076-55/+5144
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-078-7/+1629
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-0720-179/+9288
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-048-13/+4745
* [MIR] Add machine instruction lexerRichard-Qin-X2026-08-032-2/+957
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-038-21/+643
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-038-1/+600
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-0210-11/+285
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-024-0/+125
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-015-0/+143
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-014-0/+263
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-017-8/+171
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-015-0/+801
* [Support] Add MIR YAML parsing infrastructureRichard-Qin-X2026-08-013-2/+1318
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-017-36/+1259
* [CodeGen] Add target state and compilation statusRichard-Qin-X2026-08-016-0/+415
* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-018-16/+798
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-015-5/+385
* [CodeGen] Add explicit MachineFunction cloningRichard-Qin-X2026-08-012-0/+377
* [CodeGen] Add strict MachineIR verificationRichard-Qin-X2026-08-013-0/+530
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-014-70/+702
* [CMake] Match LLVM EH and RTTI defaultsRichard-Qin-X2026-08-011-10/+7
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 21:31:26 +0000