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Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-264-0/+642
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-2514-41/+438
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-259-4/+485
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-257-6/+1047
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-254-0/+522
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-258-0/+391
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-244-1/+443
* [RISCV] Implement save and restore libcallsRichard-Qin-X2026-08-243-75/+347
* [CodeGen] Match LLVM callee-save live-insRichard-Qin-X2026-08-241-1/+1
* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-244-98/+83
* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-243-209/+290
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-2410-221/+373
* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-244-297/+173
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-2411-151/+140
* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-244-1/+324
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-226-195/+145
* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-225-1/+62
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-2219-78/+830
* [CodeGen] Match LLVM final verifier contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM finalization contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM late pseudo contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-193-169/+0
* [CodeGen] Match LLVM block placement contractRichard-Qin-X2026-08-191-6/+2
* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-194-424/+304
* [CodeGen] Match LLVM tail duplication contractRichard-Qin-X2026-08-191-9/+1
* [CodeGen] Match LLVM post-machine scheduler contractRichard-Qin-X2026-08-191-7/+1
* [CodeGen] Match LLVM post-RA pseudo expansion contractRichard-Qin-X2026-08-191-7/+1
* [CodeGen] Remove non-LLVM machine DCE placementsRichard-Qin-X2026-08-191-6/+0
* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-193-24/+1
* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-192-39/+2
* [CodeGen] Match LLVM shrink wrapping contractRichard-Qin-X2026-08-191-7/+1
* [CodeGen] Match LLVM post-RA sink contractRichard-Qin-X2026-08-191-3/+1
* [CodeGen] Match LLVM post-RA LICM contractRichard-Qin-X2026-08-191-3/+1
* [CodeGen] Match LLVM post-RA combiner contractRichard-Qin-X2026-08-191-1/+1
* [CodeGen] Match LLVM stack slot coloring contractRichard-Qin-X2026-08-191-6/+1
* [CodeGen] Match LLVM PBQP allocator input contractRichard-Qin-X2026-08-191-4/+2
* [CodeGen] Match LLVM machine scheduler contractRichard-Qin-X2026-08-191-6/+1
* [CodeGen] Match LLVM machine sink input contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM prologepilog input contractRichard-Qin-X2026-08-191-2/+1
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-199-10/+760
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-1918-14/+438
* [RISCV][GlobalISel] Generate integer store selectionRichard-Qin-X2026-08-192-80/+76
* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-194-75/+310
* [RISCV][GlobalISel] Generate frame index selectionRichard-Qin-X2026-08-192-0/+17
* [RISCV][GlobalISel] Correct floating constant materializationRichard-Qin-X2026-08-191-3/+16
* [RISCV][GlobalISel] Match floating comparisonsRichard-Qin-X2026-08-195-155/+395
* [RISCV][GlobalISel] Generate trap selectionRichard-Qin-X2026-08-193-16/+28
* [RISCV][GlobalISel] Generate select instruction matchingRichard-Qin-X2026-08-195-161/+229
* [RISCV][GlobalISel] Generate indirect branch selectionRichard-Qin-X2026-08-199-22/+114
* [RISCV][GlobalISel] Generate conditional branch selectionRichard-Qin-X2026-08-176-35/+296
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 14:49:09 +0000