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* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-1210-129/+359
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-125-19/+45
* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-121-3/+73
* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-121-1/+1
* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-122-1/+87
* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-0/+77
* [clang-format] Format MIR sourcesRichard-Qin-X2026-08-122-13/+11
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-1212-78/+28
* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-123-2/+253
* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-121-1/+1
* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-2/+2
* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-122-53/+3
* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-121-6/+2
* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-2/+2
* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+4
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-122-25/+192
* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-15/+15
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-122-0/+104
* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-1/+1
* [MIR] Create virtual registers referenced by live-insRichard-Qin-X2026-08-123-6/+14
* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-122-9/+8
* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-0/+50
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-123-1/+100
* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-121-16/+33
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-4/+12
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-125-12/+44
* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-121-4/+6
* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-121-3/+4
* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-122-7/+17
* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+11
* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-2/+2
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-117-77/+183
* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-111-8/+8
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-114-55/+97
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-115-30/+14
* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-114-74/+33
* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-111-4/+10
* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-3/+123
* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-3/+2
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-115-17/+147
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-15/+49
* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-12/+11
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-111-3/+5
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-0/+94
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 14:48:04 +0000