aboutsummaryrefslogtreecommitdiff
path: root/backend/lib
Commit message (Expand)AuthorAgeFilesLines
* [GlobalISel] Remove redundant PHI narrowing checksRichard-Qin-X2026-08-291-12/+7
* [CodeGen] Complete LaneMask bitwise operationsRichard-Qin-X2026-08-283-17/+5
* [Support] Use standard power-of-two checksRichard-Qin-X2026-08-285-31/+15
* [CMake] Remove unused clang-tidy file registrationRichard-Qin-X2026-08-2818-98/+13
* [RISCV] Complete Zcmp frame lowering and optimizationRichard-Qin-X2026-08-286-209/+431
* [RISCV] Generate complete Zcmp instruction definitionsRichard-Qin-X2026-08-286-44/+217
* [CodeGen] Add target machine registryRichard-Qin-X2026-08-2813-150/+426
* [CodeGen] Separate assembly emission ownershipRichard-Qin-X2026-08-2811-859/+953
* [RISCV] Separate calling convention assignmentRichard-Qin-X2026-08-286-479/+566
* [CodeGen] Separate pass instrumentation ownershipRichard-Qin-X2026-08-284-476/+410
* [CodeGen] Remove pass instrumentation snapshotsRichard-Qin-X2026-08-281-90/+10
* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-2828-473/+145
* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-274-143/+138
* [RISCV] Generate atomic RMW selectionRichard-Qin-X2026-08-273-95/+366
* [RISCV] Remove unused selector helpersRichard-Qin-X2026-08-271-80/+0
* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-272-87/+0
* [CodeGen] Remove machine action replayRichard-Qin-X2026-08-274-172/+16
* [CodeGen] Run machine optimizations onceRichard-Qin-X2026-08-2711-215/+17
* [CodeGen] Run scheduling transformations onceRichard-Qin-X2026-08-265-136/+27
* [CodeGen] Remove transactional register allocationRichard-Qin-X2026-08-268-169/+42
* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-262-55/+18
* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-263-75/+14
* [CodeGen] Centralize machine pass property validationRichard-Qin-X2026-08-2624-169/+0
* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-269-23/+312
* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-267-4/+627
* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-267-43/+463
* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-264-0/+642
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-2514-41/+438
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-259-4/+485
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-257-6/+1047
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-254-0/+522
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-258-0/+391
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-244-1/+443
* [RISCV] Implement save and restore libcallsRichard-Qin-X2026-08-243-75/+347
* [CodeGen] Match LLVM callee-save live-insRichard-Qin-X2026-08-241-1/+1
* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-244-98/+83
* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-243-209/+290
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-2410-221/+373
* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-244-297/+173
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-2411-151/+140
* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-244-1/+324
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-226-195/+145
* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-225-1/+62
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-2219-78/+830
* [CodeGen] Match LLVM final verifier contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM finalization contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM late pseudo contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-193-169/+0
* [CodeGen] Match LLVM block placement contractRichard-Qin-X2026-08-191-6/+2
* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-194-424/+304
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 09:37:57 +0000