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* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-151-4/+3
* [RISCV] Match explicit target feature semanticsRichard-Qin-X2026-08-151-1/+3
* [MIRTool] Parse LLVM code generation optionsRichard-Qin-X2026-08-131-0/+85
* [MIRTool] Read stdin when no input path is givenRichard-Qin-X2026-08-131-2/+2
* [Tooling] Remove the duplicate output kindRichard-Qin-X2026-08-131-41/+14
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-1/+6
* [Testing] Add the LLVM MIR RUN executorRichard-Qin-X2026-08-121-0/+682
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-125-155/+176
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-124-70/+142
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-0/+19
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-112-3/+23
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-105-0/+1614