| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [MIR] Remove alternate layout and float APIs | Richard-Qin-X | 2026-08-12 | 1 | -1/+0 |
| * | [RISCV] Legalize fixed-baseline RV64 MachineIR | Richard-Qin-X | 2026-08-11 | 1 | -0/+19 |
| * | [MIR] Accept fixed-baseline LLVM syntax | Richard-Qin-X | 2026-08-11 | 2 | -3/+23 |
| * | [Tooling] Complete backend tooling and validation | Richard-Qin-X | 2026-08-10 | 7 | -70/+1617 |
| * | [MC] Implement RV64GC object emission | Richard-Qin-X | 2026-08-09 | 4 | -7/+186 |
| * | [MC] Implement RV64GC assembly emission | Richard-Qin-X | 2026-08-09 | 4 | -0/+263 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -3/+8 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -7/+15 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 3 | -0/+139 |
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