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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-1/+6
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-125-373/+0
* [Testing] Add the LLVM MIR RUN executorRichard-Qin-X2026-08-121-0/+682
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-125-155/+176
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-124-70/+142
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-121-1/+0
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-0/+19
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-112-3/+23
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-107-70/+1617
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-094-7/+186
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-094-0/+263
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-091-3/+8
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-7/+15
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-073-0/+139
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 09:37:13 +0000