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* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-0/+61
* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-111-0/+5
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-1/+25
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-114-16/+86
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-091-3/+29
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-091-2/+42
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-095-0/+1365
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-091-2/+10
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0911-2/+2364
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-094-18/+936
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-084-3/+1350
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+643
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-075-0/+2473
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+13
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-076-12/+18
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-041-6/+28
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-034-8/+406
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-032-0/+497
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-025-24/+335
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-022-0/+226
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-012-0/+283
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-012-0/+337
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-012-0/+221
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-012-0/+70
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-017-109/+1000
* [CodeGen] Add target state and compilation statusRichard-Qin-X2026-08-015-0/+666
* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-017-26/+1043
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-015-15/+294
* [CodeGen] Add explicit MachineFunction cloningRichard-Qin-X2026-08-012-0/+459
* [CodeGen] Add strict MachineIR verificationRichard-Qin-X2026-08-012-0/+474
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-012-0/+477
* [CodeGen] Add machine instruction descriptorsRichard-Qin-X2026-08-012-0/+376
* [CodeGen] Build the core MachineIR object modelRichard-Qin-X2026-08-012-0/+479
* [CodeGen] Add machine IR value semanticsRichard-Qin-X2026-08-012-5/+207
* [CodeGen] Add core machine type primitivesRichard-Qin-X2026-08-012-0/+277
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 21:57:43 +0000