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path: root/backend/unittests/Target/RISCVLateCodeGenTest.cpp
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-241-3/+8
* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-191-74/+0
* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-191-6/+5
* [CodeGen] Remove non-LLVM machine DCE placementsRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-3/+3
* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-131-83/+1
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-25/+25
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-131-1/+1
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-1/+1
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-121-21/+34
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-121-1/+1
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-121-2/+18
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-111-1/+2
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-111-1/+1
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-2/+1
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-101-1/+2
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-0/+1432
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