| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Implement RV64GC frame lowering | Richard-Qin-X | 2026-08-09 | 3 | -0/+1416 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 3 | -16/+521 |
| * | [CodeGen] Implement machine liveness analysis | Richard-Qin-X | 2026-08-09 | 1 | -2/+11 |
| * | [CodeGen] Implement machine SSA exit | Richard-Qin-X | 2026-08-08 | 2 | -0/+353 |
| * | [CodeGen] Implement RV64GC legalization and instruction selection | Richard-Qin-X | 2026-08-08 | 2 | -0/+1115 |
| * | [CodeGen] Complete machine pass and ABI lowering infrastructure | Richard-Qin-X | 2026-08-07 | 2 | -0/+809 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 2 | -23/+199 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 4 | -2/+249 |
| * | [CodeGen] Add target MIR text schema | Richard-Qin-X | 2026-08-03 | 2 | -1/+42 |
| * | [CodeGen] Add target register descriptions | Richard-Qin-X | 2026-08-01 | 3 | -0/+258 |
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