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* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-0/+37
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-0/+86
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-114-6/+6
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-101-1/+2
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-096-1/+1509
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-095-0/+235
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-094-3/+1448
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-093-0/+1416
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-093-16/+521
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-091-2/+11
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-082-0/+353
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+1115
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-072-0/+809
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-072-23/+199
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-074-2/+249
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-032-1/+42
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-013-0/+258
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 01:24:27 +0000