rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
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*	[RISCV] Preserve narrow cmpxchg results when widening	Richard-Qin-X	2026-08-11	1	-0/+37
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*	[RISCV] Legalize narrow atomic compare exchange	Richard-Qin-X	2026-08-11	1	-0/+86
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	4	-6/+6
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	1	-1/+2
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	6	-1/+1509
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	5	-0/+235
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	4	-3/+1448
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	3	-0/+1416
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	3	-16/+521
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*	[CodeGen] Implement machine liveness analysis	Richard-Qin-X	2026-08-09	1	-2/+11
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	2	-0/+353
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	2	-0/+1115
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	2	-0/+809
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	2	-23/+199
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	4	-2/+249
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[CodeGen] Add target MIR text schema	Richard-Qin-X	2026-08-03	2	-1/+42
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*	[CodeGen] Add target register descriptions	Richard-Qin-X	2026-08-01	3	-0/+258
	Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.