rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[CodeGen] Track reserved register defs precisely	Richard-Qin-X	2026-08-12	1	-3/+25
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*	[CodeGen] Test cloning unnamed functions	Richard-Qin-X	2026-08-12	1	-5/+5
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*	[RISCV] Model dynamic rounding-mode state	Richard-Qin-X	2026-08-12	1	-7/+15
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*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	2	-6/+29
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*	[MIR] Ignore empty YAML documents	Richard-Qin-X	2026-08-12	1	-0/+31
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*	[RISCV] Describe the GPR select pseudo	Richard-Qin-X	2026-08-12	1	-1/+1
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*	[CodeGen] Accept pointer comparisons in G_ICMP	Richard-Qin-X	2026-08-12	1	-1/+12
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*	[RISCV] Model target-specific generic opcodes	Richard-Qin-X	2026-08-12	1	-1/+1
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*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	2	-3/+51
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*	[MIR] Accept physical-only function live-ins	Richard-Qin-X	2026-08-12	1	-2/+3
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*	[MIR] Accept unnamed stack objects	Richard-Qin-X	2026-08-12	1	-1/+2
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*	[MIR] Accept empty optional register fields	Richard-Qin-X	2026-08-12	1	-2/+3
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*	[CodeGen] Treat reserved registers as always live	Richard-Qin-X	2026-08-11	1	-0/+41
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*	[CodeGen] Accept conservative physical live-ins	Richard-Qin-X	2026-08-11	1	-0/+6
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*	[RISCV] Model typed floating-point register views	Richard-Qin-X	2026-08-11	7	-78/+120
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*	[RISCV] Order call operands like LLVM MIR	Richard-Qin-X	2026-08-11	1	-7/+20
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*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	4	-13/+47
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*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	4	-10/+4
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*	[RISCV] Derive the generated instruction count in tests	Richard-Qin-X	2026-08-11	1	-1/+5
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*	[RISCV] Match LLVM call-frame pseudo semantics	Richard-Qin-X	2026-08-11	2	-11/+47
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*	[RISCV] Use canonical copies for full ABI values	Richard-Qin-X	2026-08-11	1	-3/+5
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*	[RISCV] Lower multiply without M through libcalls	Richard-Qin-X	2026-08-11	1	-0/+59
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*	[RISCV] Accept generic scalars in call lowering	Richard-Qin-X	2026-08-11	1	-0/+16
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*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	1	-0/+19
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*	[RISCV] Fold narrow binary artifact chains	Richard-Qin-X	2026-08-11	1	-0/+69
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*	[CodeGen] Revisit instructions invalidated by legalization	Richard-Qin-X	2026-08-11	1	-0/+61
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*	[RISCV] Preserve folded constant placement	Richard-Qin-X	2026-08-11	1	-3/+20
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*	[RISCV] Reuse compare operand extensions	Richard-Qin-X	2026-08-11	1	-0/+43
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*	[RISCV] Legalize integer compares to RV64 containers	Richard-Qin-X	2026-08-11	1	-16/+53
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*	[RISCV] Preserve live constants when folding extensions	Richard-Qin-X	2026-08-11	1	-0/+49
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*	[MIR] Omit absent zero-offset MMO bases	Richard-Qin-X	2026-08-11	1	-2/+9
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*	[RISCV] Lower cmpxchg with success	Richard-Qin-X	2026-08-11	1	-1/+37
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*	[RISCV] Preserve narrow cmpxchg results when widening	Richard-Qin-X	2026-08-11	1	-0/+37
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*	[RISCV] Legalize narrow atomic compare exchange	Richard-Qin-X	2026-08-11	1	-0/+86
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*	[MIR] Parse one-ordering compare-exchange MMOs	Richard-Qin-X	2026-08-11	2	-9/+52
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	5	-7/+31
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*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	12	-21/+318
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	11	-1/+1195
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	10	-6/+2060
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	10	-2/+436
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	10	-3/+2823
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	5	-2/+1428
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	14	-18/+2885
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*	[CodeGen] Implement machine liveness analysis	Richard-Qin-X	2026-08-09	6	-21/+949
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	6	-3/+1703
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	4	-0/+1758
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	7	-0/+3282
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	2	-23/+199
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	5	-2/+262
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[MIR] Complete document parsing and printing	Richard-Qin-X	2026-08-07	11	-14/+1566
\| \| \| \|	Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.